5–7 Jul 2012
ETH Zürich
Europe/Zurich timezone

Development of energy dispersive detectors at STFC

5 Jul 2012, 15:00
25m
F7 (ETH Zürich)

F7

ETH Zürich

Energy dispersive detectors Energy dispersive detectors

Speaker

Mr Matt Wilson (STFC Detector Development Group)

Description

A hyperspectral imaging detector for high energy X-rays has been developed at STFC as part of the UK wide HEXITEC collaboration. The HEXITEC detector uses CdTe or CdZnTe with 80x80 pixels on a 250µm pitch. Each pixel is gold stud and silver epoxy bump bonded onto the HEXITEC ASIC which has a set of identical electronics to readout the energy of every photon detected in the sensor from 4keV to 200keV. The pixel electronics contain a charge sensitive pre-amplifier with leakage current compensation; a two stage shaping amplifier and a peak hold circuit. The peak hold voltages, which are directly proportional to the energy of the detected photons, are sequentially readout using a rolling row readout method with a frame rate of 10kHz. The voltages are digitized and have some basic processing in a data acquisition system before being sent to a dedicated PC over base camera link. The data is calibrated and charge sharing corrections are applied to the data to allow the best energy resolution to be obtained. With 1mm thick Schottky contact CdTe an average pixel energy resolution (FWHM) of 0.8keV at 60keV is achieved with room temperature operation. To be able to identify and correct the charge sharing events there needs to be ≈10% or fewer pixels with an event in anyone frame. This dictates that the maximum number of photons that can be measure with high energy resolution is limited to 10million photons/80x80 detector/second. The HEXITEC 80x80 detector has an active area of 2x2cm but it can be butted on three sides. Results from a 2x2 tiled array of HEXITEC detectors will be presented as well as designs for larger area detectors using the three side buttable design. Four side buttable HEXITEC ASICs have been manufactured with a post processing method of forming thru silicon vias to place the wire bond pads on the back side of the ASIC. The processing method and results and the HEXITEC ASICs will also be presented.

Primary author

Mr Matt Wilson (STFC Detector Development Group)

Co-authors

Dr Andreas Schneider (STFC Detector Development Group) Ms Christiana Chrisodoulou (UCL) Dr Christopher Egan (University of Manchester) Dr Daniel O'Flynn (UCL) Dr James Scuffham (Royal Surrey County Hospital) Mr Lawrence Jones (STFC ASIC Design Group) Mr Marcus French (STFC Front End Systems) Mr Mark Prydderch (STFC ASIC Design Group) Dr Matthew Veale (STFC Detector Development Group) Mr Paul Seller (STFC Detector Development Group) Prof. Robert Cernik (University of Manchester) Prof. Robert Speller (UCL) Dr Silvia Pani (University of Surrey) Dr Simon Jacques (University of Manchester) Mr Stephen Thomas (STFC ASIC Design Group) Mr Steven Bell (STFC Detector Development Group)

Presentation materials