Oct 9 – 13, 2022
FHNW Campus Brugg-Windisch
Europe/Zurich timezone

Clock and LO Phase Noise Correlation Effects on RF Sampling

Oct 12, 2022, 2:52 PM
Lichthof (Building 1)


Building 1

Poster Low Level RF Workshop 2022 Poster Session


Maciej Grzegrzółka (Institute of Electronic Systems, Warsaw University of Technology)


Sampling the RF signals is a challenging problem for the modern LLRF Control System. One of the analog-to-the digital conversion problems is the clock jitter's influence on the output signal. As clock jitter impact increases with the input signal frequency, it is primarily a problem in precise RF systems, where signal frequencies are high. This issue can be minimized by lowering the input signal frequency using the down-converter circuit. This approach increases the complicity of the RF front-end and requires the generation of an additional Local Oscillator (LO) signal.

Reducing the noise introduced in the digitizer circuit is essential in a high-performance system. Phase noises of both the LO and clock signals contribute to it. The most obvious method of improving the performance is reducing the absolute values of both signals' phase jitter. Because phase noises of LO and clock signals are mostly non-deterministic, it is also very likely that the correlation between the phase noises of those signals matters. This contribution investigates the impact of the correlation between clock and LO signals phase noises on the digitizer circuit noise performance.

Primary authors

Krzysztof Czuba (Institute of Electronic Systems) Maciej Grzegrzółka (Institute of Electronic Systems, Warsaw University of Technology) Mr Šerlat Andžej (Institute of Electronic Systems, Warsaw University of Technology)

Presentation materials