The superconducting cavity vertical test stand at DESY is going to be updated with the MTCA.4 based system. The digital self exited loop (SEL) LLRF controller has been developed to fulfill the requirements for the controller to drive the cavity with high QL up to 1e10 and high cavity detuning up to 10kHz. In order to test the SEL controller, additionally the real-time cavity simulator has been developed. The electrical and mechanical model of a cavity represented by a differential equation, is implemented inside the FPGA. The model takes the forward power as an input and produces a probe signal based on given detuning and half-bandwidth parameters of a cavity. Microphonic disturbance is also added to simulate the high Ql operation.
Both, the cavity simulator and the SEL controller have been implemented in the SIS8300KU, DRTM-DW8VM1 pair boards.